California NanoSystems Institute
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Jason Woo, Ph.D.

Professor, Electrical Engineering
Member, NanoElectronics, Photonics, Architectonics, California NanoSystems Institute

Ph.D., Stanford University, 1987

Honors and Awards:
1988 - 1990 IBM Faculty Development Award
1981 W.S. Wilson Medal
1980 - 1981 Andrew A. Kinghorn Scholarship
1980 J. Edgar McAllister Summer Research Fellowship
1979 - 1980 Andrew A. Kinghorn Scholarship
1977 - 1979 Reuben Wells Leonard Scholarship

Professional Societies:
IEEE, Fellow

Contact Information:
Email Address:
Work Email Address:
Work Address: UCLA
Department of Electrical Engineering
Box 951594
Los Angeles, CA 90095
Home Page:
Fax Number: (310) 206-8495
Office Phone Number: (310) 794-4077
Work Phone Number: (310) 206-3279
Research Interests:

Solid-state technology, device physics, MOS and bipolar device characteristics at low temperatures, modeling of integrated circuits, VLSI fabrication.

Additional Information:

Jason C.S. Woo received the B.A.Sc. (Hons.) degree in engineering science from the University of Toronto, Canada, in 1981, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1982 and 1987, respectively. He joined the UCLA Electrical Engineering Department in 1987 and is currently a professor.

Prof. Woo served on the IEEE IEDM program committee from 1989-1990 and 1994-1996, and was the publicity vice-chairman in 1992 and the publicity chairman in 1993. He is the workshop chairman and has been a technical committee member of the VLSI Technology Symposium since 1992. Since 1993, he has been on the IEEE SOI conference committee and was the technical program chairman for the conference in 1999. He has also been appointed recently to serve as the chair of IEEE electronic device society ad hoc committee on short courses.

Prof. Woo's research interests are in the physics and technology of novel device and device modeling. He has done work on low temperature device for VLSI and space applications, SOI BiCMOS and GeSi BiCMOS. Significant achievements include the analysis and fabrication of cryogenic Bipo-lar transistors, the identification of hot-carrier reliability failure modes at reduced temperatures, the first demonstration of GeSi quantum-well MOSFETs, and the investigation of device physics/technology for deep submicron SOI CMOS. He has also worked on technology such as drain engineering and alternative gate dielectrics to improve CMOS performance and reliability.

Prof. Woo received the IBM Faculty Development Award from 1987-1989. He has authored or coauthored over 100 papers in technical journals and refereed conference proceedings in these areas.

Selected Publications:

Wei Liu, Choong-Heui Chung, Cong-Qin Miao, Yan-Jie Wang, Bi-Yun Li, Ling-Yan Ruan, Ketan Patel, Young-Ju Park, Jason Woo and Ya-Hong Xie, Chemical vapor deposition of large area few layer graphene on Si catalyzed with nickel films, Thin Solid Films, 2010, 518 (6, S1), S128-S132.
Yu-Lin Chao and Jason C. S. Woo, Germanium n+/p diodes: a dilemma between shallow junction formation and reverse leakage current control, IEEE Transactions on Electron Devices, 2010, 57 (3), 665-70.
Liu W, Jackson BL, Zhu J, Miao CQ, Chung CH, Park YJ, Sun K, Woo J, Xie YH, Large scale pattern graphene electrode for high performance in transparent organic single crystal field-effect transistors, ACS Nano, 2010, 4 (7), 3927-32.
Tura, A.; Woo, J., Performance Comparison of Silicon Steep Subthreshold FETs, IEEE Transactions on Electron Devices, 2010, 57 (6), 1362-8.
Yanjie Wang; Congqin Miao; Bo-chao Huang; Jing Zhu; Wei Liu; Youngju Park; Ya-hong Xie; Jason Woo, Scalable Synthesis of Graphene on Patterned Ni and Transfer, IEEE Transactions on Electron Devices, 2010, 57 (12), 3472-6.
Zhu, J.; Jhaveri, R.; Woo, J.C.S., The effect of traps on the performance of graphene field-effect transistors, Appl. Phys. Lett, 2010, 96 (19), 193503-1-3.
Mecklenburg, M., Woo, J., and Regan, B. C., Tree-level electron-photon interactions in graphene, Physical Review B, 2010, 81 (24).
Jhaveri, R. Nagavarapu, V. Woo, J. C. S., Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications, Ieee Transactions on Electron Devices, 2009, 56 (1), 93-99.
Jing Zhu, Jason C.S. Woo, Graphene Channel Field-Effect Transistors with Schottky Tunneling Source and Drain, 2009 International Conference on Solid State Devices and Materials, 2009, 1226-1227.
Venkatagirish, N.; Tura, A.; Jhaveri, R.; Hsu-Yu Chang; Woo, J., The Tunnel Source MOSFET: A Novel Asymmetric Device Solution for Ultra-low Power Applications, 2009 IEEE International Conference on IC Design and Technology, 2009, 155-159 .
Venkatagirish N., Ahmet Tura, Ritesh Jhaveri, Hsu-Yu Chang, Jason Woo, The Tunnel Source n-MOSFET: A Novel Asymmetric Device for Low Power Applications, 2009 International Conference on Solid State Devices and Materials, 2009, 20-21.
Nagavarapu, V. Jhaveri, R. Woo, J. C. S., The tunnel source (PNPN) n-MOSFET: A novel high performance transistor, Ieee Transactions on Electron Devices, 2008, 55 (4), 1013-1019.
Jintae Kim; Jhaveri, R.; Woo, J.; Chih-Kong Ken Yang, Device-circuit co-optimization for mixed-mode circuit design via geometric programming, IEEE/ACM International Conference on Computer-Aided Design, 2007, 470-475.
Schipper, M. L. Cheng, Z. Lee, S. W. Bentolila, L. A. Iyer, G. Rao, J. H. Chen, X. Y. Wul, A. M. Weiss, S. Gambhirl, S. S., MicroPET-based biodistribution of quantum dots in living mice, Journal of Nuclear Medicine, 2007, 48 (9), 1511-1518.
Yu-Lin, Chao Woo, J. C. S., Source/drain engineering for parasitic resistance reduction for germanium p-MOSFETs, IEEE Transactions on Electron Devices, 2007, 54 (10), 2750-2755.
Yu-Lin, Ghao Scholz, R. Reiche, M. Gosele, U. Woo, J. C. S., Characteristics of germanium-on-insulators fabricated by wafer bonding and hydrogen-induced layer splitting, Japanese Journal of Applied Physics, Part 1 (Regular Papers, Short Notes & Review Papers), 2006, 45 (11), 8565-8570.
Chao, Y. L. Xu, Y. Scholz, R. Woo, J. C. S., Characterization of copper germanide as contact metal for advanced MOSFETs, Ieee Electron Device Letters, 2006, 27 (7), 549-551.
Jun Yuan, Jason C. S. Woo, "A Novel Split Gate MOSFET Design Realized By a Fully Silicided Gate Process for the Improvement of Trans-conductance and Output Resistance", IEEE Elec. Dev. Lett, 2005.
D. Dimitripoulos, R. Jhaveri, R. Claps, J. C. S. Woo and B. Jalali, "Carrier Lifetime in Silicon Raman Laser", Applied Physics Letters, 2005, 86.
Seong-Dong Kim, Cheol-Min Park and Jason C.S. Woo, "Formation and control of box-shaped ultra-shallow junction using laser annealing and pre-amorphization implantation", Solid-State Electronics, 2005, 49 (1), 131-135.
Y.-L. Chao, Q.-Y. Tong, T.-H. Lee, M. Reiche, R. Scholz, J. C.-S. Woo, U. Goesele, "NH4OH Effects on Low Temperature Bonding Energy Enhancement.", Electrochemical and Solid State Letters (Accepted), 2005.
Jun Yuan, Jason C. S. Woo, "Tunable work function in fully nickel silicided polysilicon gates for metal gate MOSFET applications", IEEE Elec. Dev. Lett, 2005, 26 (2), 87-89.
Jun, Yuan Woo, J. C. S., A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance, IEEE Electron Device Letters, 2005, 26 (11), 829-831.
Chao, Y. L. Tong, Q. Y. Lee, T. H. Reiche, M. Scholz, R. Woo, J. C. S. Gosele, U., Ammonium hydroxide effect on low-temperature wafer bonding energy enhancement, Electrochemical and Solid State Letters, 2005, 8 (3), G74-G77.
Dimitropoulos, D. Jhaveri, R. Claps, R. Woo, J. C. S. Jalali, B., Lifetime of photogenerated carriers in silicon-on-insulator rib waveguides, Applied Physics Letters, 2005, 86 (7), 3.
Yuan, J. Pan, G. Z. Chao, Y. L. Woo, J. C. S., Nickel silicide work function tuning study in metal-gate CMOS applications, Progress in Compound Semiconductor Materials IV-Electronic and Optoelectronic Applications. Symposium, 2005, volume (number), 319-324.
Chao, Y. L. Prussin, S. Woo, J. C. S. Scholz, R., Preamorphization implantation-assisted boron activation in bulk germanium and germanium-on-insulator, Applied Physics Letters, 2005, 87 (14), 3.
Hakim, N. U. D. Rao, V. R. Vasi, J. Woo, J. C. S., Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET, in analog applications, Ieee Transactions on Device and Materials Reliability, 2005, 5 (1), 127-132.
Suryagandh, S.S., Garg, M., Woo, J.C.S., "A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs", IEEE Transactions on Electron Devices, 2004, 51 (7), 1122-28.
Seong-Dong Kim, Wada, H., Woo, J.C.S. , "TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling", IEEE Transactions on Semiconductor Manufacturing, 2004, 17 (2), 192-200.
Jun, Yuan Woo, J. C. S., Nanoscale MOSFET with split-gate design for RF/analog application, Japanese Journal of Applied Physics, Part 1 (Regular Papers, Short Notes & Review Papers), 2004, 43 (4B), 1742-1745.
Suryagandh, S. S. Garg, M. Woo, J. C. S., A detailed analysis of SOI MOSFETs for SOC design, 2003 IEEE International SOI Conference. Proceedings, 2003, 147-148.
Seong-Dong Kim, Cheol-Min Park, Woo JCS, "Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. II. Quantitative analysis", IEEE Transactions on Electron Devices, 2002, 49 (3), 467-72.
Seong-Dong Kim, Cheol-Min Park, Woo JCS, "Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS", IEEE Transactions on Electron Devices, 2002, 49 (10), 1748-54.
Najeev-ud-din, Dunga MV, Kumar A, Vasi J, Ramgopal Rao V, Baohong Cheng, Woo JCS, "Analysis of floating body effects in thin film conventional and single pocket SOI MOSFETs using the GIDL current technique", IEEE Electron Device Letters, 2002, 23 (4), 209-11.
Deshpande HV, Baohong Cheng, Woo JCS, "Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications", IEEE Transactions on Electron Devices, 2002, 49 (9), 1558-65.
Borse DG, Rani KN M, Jha NK, Chandorkar AN, Vasi J, Ramgopal Rao V, Cheng B, Woo J. C .S. , "Optimization and realization of sub-100-nm channel`length single halo p-MOSFETs", IEEE Transactions on Electron Devices, 2002, 49 (6), 1077-9.