California NanoSystems Institute
CNSI
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Jason Cong, Ph.D.

   
Chair and Professor, Computer Science
Member, NanoElectronics, Photonics, Architectonics, California NanoSystems Institute

Education:
Degrees:
Ph.D., University of Illinois at Urbana-Champaign, 1990
Fellowships:
2000 IEEE, IEEE Fellow
1988 DEC, Fellowship in Computer Science

Honors and Awards:
2005 ACM Transaction on Design Automation of Electronic Systems (TODAES), Best Paper Award
2005 2005 International Symposium on Physical Design (ISPD), Best Paper Award
2004 - 2005 IEEE Circuits and Systems Society, Distinguished Lecturer
2000 Semiconductor Research Corporation, Inventor Recognition Award
2000 Peking University, Guest Professorship
2000 Semiconductor Research Corporation, Technical Excellence Award
1998 ACM SIGDA, Meritorious Service Award
1997 ACM, Recognition of Service Award
1995 IEEE Transactions on Computer-Aided Design from IEEE Circuits and System Society, Best Paper Award
1993 Northrop Corporation, Outstanding Junior Faculty Research Award from UCLA
1991 National Science Foundation, Engineering Research Initiation Award
1989 University of Illinois, Ross J. Martin Award for Excellence in Research
1985 Peking University, Best Graduate Award

Certifications:
Certification Type:
1993 National Science Foundation, Young Investigator Award

Contact Information:
Email Address: cong@cs.ucla.edu
Work Address: BOX 951596, 4731J BH
Mail Code: 159610
Los Angeles, CA 90095
UNITED STATES
Home Page: http://cadlab.cs.ucla.edu/~cong/
Fax Number: 310-825-2273
Office Phone Number: (310) 825-8145
Work Phone Number: (310) 206-2775
Research Interests:

Dr. Cong’s research interests include computer-aided design of nano-scale electronics, design of system-on-a-chip, programmable systems, novel computer architectures, and nano-systems. He has published over 300 research papers and led over 30 research projects supported by DARPA, NSF, SRC, and a number of industrial sponsors in these areas.


Additional Information:

Dr. Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Dr. Cong received a number of awards and recognitions, include the Best Graduate Award from Peking University in 1985, and the Ross J. Martin Award for Excellence in Research from the University of Illinois at Urbana-Champaign in 1989, the NSF Young Investigator Award in 1993, the Northrop Outstanding Junior Faculty Research Award from UCLA in 1993, the ACM/SIGDA Meritorious Service Award in 1998, and the SRC Technical Excellence Award in 2000. He also received four best paper awards—including the 1995 IEEE Trans. on CAD Best Paper Award, the 2005 International Symposium on Physical Design Best Paper Award, the 2005 ACM Transaction on Design Automation of Electronic Systems Best Paper Award, and the 2008 International Symposium on High Performance Computer Architecture (HPCA), respectively. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008. Dr. Cong has served on the Technical Advisory Board of a number of EDA and silicon IP companies, including Atrenta, eASIC, Get2Chip, Magma Design Automation, and Ultima Interconnect Technologies. He was the founder and president of Aplus Design Technologies, Inc., until it was acquired by Magma Design Automation in 2003. He served as the Chief Technology Advisor of Magma from 2003 to 2008. Currently, he is the Chief Technology Advisor for AutoESL Design Technologies, Inc., a recent start-up that licensed UCLA research in the area of high-level and system-level synthesis for electronic systems for commercialization. Dr. Cong has graduated 24 PhD students. A number of them are now faculty members in major research universities, including Georgia Tech., Purdue, SUNY Binghamton, UCLA, UIUC, and UT Austin. Others are taking key R&D or management positions in major EDA/computer/semiconductor companies, such as Broadcom, Cadence, IBM, Intel, Magma, and Synopsys, or being founding members of high-tech startups, such as Aplus and AutoESL Design Technologies.

Selected Publications:

Chen DM, Cong J, Fan YP, Wan L, LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (4), 564-577.
Robert Brayton, Jason Cong, NSF Workshop on EDA: Past, Present, and Future (Part 1), IEEE DESIGN & TEST OF COMPUTERS, 2010, 27 (2), 68-74.
Brayton R, Cong J, NSF Workshop on EDA: Past, Present, and Future (Part 2), IEEE DESIGN & TEST OF COMPUTERS , 2010, 27 (3), 62-74.
Cong J., Luo G. , A Multilevel Analytical Placement for 3D ICs, Proceedings of the 14th Asia and South Pacific Design Automation Conference , 2009, 361-366.
Cong J., Minkovich K., Logic Synthesis for Better Than Worst-case Designs, Proceedings International Symposium on VLSI Design, Automation and Test, 2009.
Cong J., Gupta P., Lee J., On the Futility of Statistical Power Optimization, Proceedings of the 14th Asia and South Pacific Design Automation Conference, 2009, 167-172.
Jason Cong, Yiping Fan, Junjuan Xu , Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2009, 14 (3).
Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang, Synthesis Algorithm for Application-Specific Homogeneous Processor Networks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17 (9), 1318-1329 .
Jason Cong, Wolfgang Rosenstiel, The Last Byte: The HLS tipping point, IEEE DESIGN & TEST OF COMPUTERS, 2009, 26 (4), 104.
Cong, J. Xie, M., A robust mixed-size legalization and detailed placement algorithm, Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27 (8), 1349-1362.
Cong, J. Luo, G. J. Radke, E., Highly Efficient Gradient Computation for Density-Constrained Analytical Placement, IEEE Transactions On Computer-Aided Design of Integrated Circuits And Systems , 2008, 27 (12), 2133-2144 .
Ma, Y. C. Liu, Y. X. Kursun, E. Reinman, G. Cong, J., Investigating the Effects of Fine-Grain Three-Dimensional Integration on Microarchitecture Design, Acm Journal on Emerging Technologies in Computing Systems, 2008, 4 (4), 30.
X. Li, Y. Ma, X. Hong, S. Dong, J. Cong, Lp based white Space Redistribution for Thermal Via Planning and Performance Optimization in 3D ICs, Proc. Asia and South Pacific Design Automation Conference , 2008, 209-212.
M.-C.F. Chang, E. Socher, S.-W. Tam, J. Cong, G. Reinman, RF Interconnects for Communications On-Chip, Proceedings of the 2008 ACM International Symposium on Physical Design, 2008, 78-83.
Jason Cong, John Lee, and Lieven Vandenberghe, Robust Gate Sizing via Mean Excess Delay Minimization, Proceedings of the 2008 ACM International Symposium on Physical Design , 2008, 10-14.
J. Cong and J. Xu, Simultaneous FU and Register Binding Based on Network Flow Method, Design, Automation and Test in Europe , 2008, 1057-1062.
Xie, Y. Cong, J. Franzon, P., Special Issue on 3D Integrated Circuits and Microarchitectures, Acm Journal on Emerging Technologies in Computing Systems, 2008, 4 (4), 2.
J. Cong, Y. Ma, Y. Liu, E. Kursun, G. Reinmann, 3D Architecture Modeling and Exploration, Proceedings of 24th International VLSI?ULSI Multilevel Interconnection Conference, 2007, 231-238.
Cong, J. Han, G. L. Jagannathan, A. Reinman, G. Rutkowski, K., Accelerating sequential applications on CMPs using core spilling, Ieee Transactions on Parallel and Distributed Systems, 2007, 18 (8), 1094-1107.
Y. Liu, Y. Ma, E. Kursun, G. Reinman, Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration, Proc. IEEE International Conference on Computer Designs, 2007, 259-266.
Cong, J. Minkovich, K., Optimality study of logic synthesis for LUT-based FPGAs, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2007, 26 (2), 230-239.
Li, C. Xie, M. Koh, C. K. Cong, J. Madden, P. H., Routability-driven placement and white space allocation, Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26 (5), 858-871.
J. Cong, G. Han and Z. Zhang, Architecture and Compiler Optimization for Data Bandwidth Improvement in Configurable Processors, IEEE Transaction on Very Large Scale Integration Systems, 2006, 14 (9), 986-997.
J. Cong, M. Romesis and J.R. Shinnerl, Fast floorplanning by look-ahead enabled recursive bipartitioning, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25 (9), 1719-1732.
D. Chen, J. Cong, and J. Xu, Optimal Simultaneous Module and Multi-Voltage Assignment for Low-Power, ACM Transaction on Design Automation of Electronic Systems, 2006, 11 (2), 362-386.
G. Chen and J. Cong, Simultaneous Placement with Clustering and Duplication, ACM Transaction on Design Automation of Electronic Systems, 2006, 11 (3), 740-772.
J. Cong, T. Kong, J. Shinnerl, M. Xie and X. Yuan, "Large Scale Circuit Placement ", ACM Transactions on Design Automation of Electronic Systems, 2005, 10 (2), 389-430.
J. Cong, J. Fang, M. Xie and Y. Zhang, "MARS A Multilevel Full-Chip Gridless Routing System", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24 (3), 382-394.
J. Cong, D. Chen, L. He, F. Li and Y. Lin, "Power Modeling and Characteristics of Field Programmable Gate Arrays", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24 (11), 1712-1724.
J. Cong, H. Huang and X. Yuan, "Technology Mapping and Architecture Evaluation for k/m-Macrocell-Based FPGAs", ACM Transaction on Design Automation of Electronic Systems, 2005, 10 (1), 3-23.
J. Cong, Y. Fan, G. Han, X. Yang and Z. Zhang, "Architecture and Synthesis for On-Chip Multicycle Communication", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 23 (4), 550-564.
J. Cong, and S. K. Lim, "Edge Separability-based Circuit Clustering With Application to Multi-level Circuit Partitioning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 23 (3), 346-357.
C.-C. Chang, J. Cong, M. Romesis and M. Xie, "Optimality and Scalability Study of Existing Placement Algorithms", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 537-549.
J. Cong and S. K. Lim, "Retiming-based Timing Analysis with an Application to Mincut-based Global Placement", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 23 (12), 1684-1692.
C.-C. Chang, J. Cong, D. Pan and X. Yuan, "Multilevel Global Placement with Congestion Control", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22 (4), 395-409.
D. Chen, J. Cong M. Ercegovac and Z. Huang, "Performance-Driven Mapping for CPLD Architectures", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22 (4), 1424-1431.
T. Uchino and J. Cong, "An Interconnect Energy Model Considering Coupling Effects", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21 (7), 763-776.
J. Cong and Z. Pan, "Wire Width Planning for Interconnect performance Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21 (3), 319-329.