California NanoSystems Institute
CNSI
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Chi On Chui, Ph.D.

   
Associate Professor, Electrical Engineering
Member, California NanoSystems Institute

Education:
Degrees:
Ph.D., Stanford University, 2004
M.S., Stanford University, 2001
B.Sc., Hong Kong University of Science and Technology, 1999

Honors and Awards:
2010 IEEE, The 25th Int. on Symp. Defect and Fault Tolerance in VLSI Syst. (DFT’10) Best Student Paper Award
2009 IEEE, Electron Devices Society Early Career Award
2007 Okawa Foundation, Research Grant
2004 The 13th Workshop on Dielectrics in Microelectronics (WoDiM) Best Paper Award
2002 IEEE, The 60th Device Research Conference (DRC) Best Student Paper Award
1999 Hong Kong University of Science and Technology, Academic Achievement Medal

Certifications:
Certification Type:
2008 - IEEE, Senior Member

Contact Information:
Work Email Address: chui@ee.ucla.edu
Office Address: 6730B Boelter Hall
UCLA
Los Angeles, CA 90095
UNITED STATES
Home Page: http://www.ee.ucla.edu/faculty-chui.htm
Work Phone Number: 310-267-4786
Technical Research Interest:

Prof. Chui’s current research focuses on developing top-down and bottom-up nanotechnology for nanoarchitectonics, biomedical electronics, nanoelectronics, and terahertz electronics.


Additional Information:

Chi On Chui received the B.Eng. degree in Electronic Engineering (with highest honors) from the Hong Kong University of Science and Technology (HKUST) in 1999, and the M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 2001 and 2004, respectively. He joined the Intel Corporation as a Senior Device Engineer in 2004 to research and evaluate post-silicon transistor technologies for high performance logic applications. During his tenure with Intel, he served as a Researcher-in-Residence at the University of California, Berkeley and at Stanford University. From 2005-2006, he was also appointed Consulting Assistant Professor of Electrical Engineering at Stanford University. In January 2007, he joined the faculty of the University of California, Los Angeles (UCLA) as an Assistant Professor of Electrical Engineering. Since 2009, he has been an elected Member of the UCLA’s California NanoSystems Institute (CNSI). Dr. Chui is a Senior Member of the IEEE and a past member of the Materials Research Society (MRS). He has served on the International Advisory Committee of the International Symposium on Advanced Fluid Information and Transdisciplinary Fluid Integration (AFI/TFI) and the IEEE International Conference on Computer, Control & Communication (IEEE-IC4). He also served on the Technical Program Committee of the IEEE International Electron Devices Meeting (IEDM) and IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Selected Publications:

Kim J, Hong AJ, Kim SM, Shin KS, Song EB, Hwang Y, Xiu F, Galatsis K, Chui CO, Candler RN, Choi S, Moon JT, Wang KL, A stacked memory device on logic 3D technology for ultra-high-density data storage, Nanotechnology, 2011, 22 (25), 254006.
K.-H. Shih and C. O. Chui, High Mobility Compound Semiconductor Permeable Base Transistors with Suppressed Base Current, Electrochem. Soc. Trans, 2010, 33.
C. O. Chui and K.-H. Shih, High Mobility III-V Permeable Base Transistors with Suppressed Base Current, Proc. 218th Mtg. Electrochem. Soc, 2010, Paper E12-1768.
G. Leung and C. O. Chui, Impact of Line Edge Roughness and Device Scaling on Double-Gate FinFET Variability, The 4th IEEE Int. Wrkshp. DFM&Y, 2010.
A. Pan, D.-S. Pan, and C. O. Chu, Mechanism for Excess Noise in Mixed Tunneling and Avalanche Breakdown of Silicon, Appl. Phys. Lett, 2010, 96, 263503.
P. Narayanan, M. Leuchtenburg, J. Kina, P. Joshi, P. Panchapakeshan, C. O. Chui, and C. A. Moritz, Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration, The 25th IEEE Int. on Symp. Defect and Fault Tolerance in VLSI Syst. (DFT?10), 2010.
H. S. Yu and C. O. Chui, Insights and Optimizations of Tunnel Field-Effect Transistor Operations, IEEE 67th Dev. Res. Conf. (DRC) Dig, 2009, 87-88.
P. Narayanan, K. W. Park, C. O. Chui, and C. A. Moritz, Manufacturing Pathway and Associated Challenges for Nanoscale Computational Systems, IEEE 9th Int. Conf. Nanotechnol. (IEEE NANO 2009), 2009.
K.-S. Shin, K. Lee, J. Y. Kang, and C. O. Chui, Novel T-Channel Nanowire FET with Built-in Signal Amplification for pH Sensing, IEEE Int. Electron Dev. Mtg. (IEDM) Tech. Dig, 2009, 599-602.
P. Narayanan, C. A. Moritz, K. W. Park, and C. O. Chui, Validating Cascading of Crossbar Circuits with an Integrated Device-Circuit Exploration, IEEE/ACM Int. Symp. Nanoscale Archit. (NANOARCH 2009), 2009, 37-42.
P. T. Chen, Y. Sun, E. Kim, P. C. McIntyre, W. Tsai, M. Garner, P. Pianetta, Y. Nishi, and C. O. Chui, HfO2 Gate Dielectric on (NH4)2S Passivated (100) GaAs Grown by Atomic Layer Deposition, Journal of Applied Physics, 2008, 103 (3), 034106.
K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, K. C. Saraswat, H. E. Maes, and G. Groeseneken, On the Correct Extraction of Interface Trap Density of MOS Devices with High-Mobility Semiconductor Substrates, IEEE Transactions on Electron Devices, 2008, 55 (2), 547-556.
K.-H. Shih and C. O. Chui, The Low Subthreshold Swing Possibility with Asymmetries in Double-Gate SOI MOSFET, Proc. 2008 IEEE Int. SOI Conf, 2008, 53-54.
N. Goel, P. Majhi, C. O. Chui, W. Tsai, D. Choi, and J. S. Harris, InGaAs Metal- Oxide-Semiconductor Capacitors with HfO2 Gate Dielectric Grown by Atomic-Layer Deposition, Applied Physical Letters, 2006, 89 (16), 163517.
A. K. Okyay, C. O. Chui, and K. C. Sarawat, Leakage Suppression by Asymmetric Area Electrodes in Metal-Semiconductor-Metal Photodetectors, Applied Physical Letters, 2006, 88 (6), 063505.
C. O. Chui, F. Ito, and K. C. Saraswat, Nanoscale Germanium MOS Dielectrics―Part I: Germanium Oxynitrides, IEEE Trans. Electron Devices, 2006, 53 (7), 1501-1508.
C. O. Chui, H. Kim, D. Chi, P. C. McIntyre, and K. C. Saraswat, Nanoscale Germanium MOS Dielectrics―Part II: High-k Gate Dielectrics, IEEE Trans. Electron Devices, 2006, 53 (7), 1509-1516.
H. Lan, T. W. Chen, C. O. Chui, P. Nikaeen, J. W. Kim, and R. W. Dutton, Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs, IEEE J. of Solid-State Circuits (Special Issue on the IEEE 2005 Custom Integr. Circuit Conf.), 2006, 41 (8), 1817-1829.
C.-H. Lu, G. M. T. Wong, M. D. Deal, W. Tsai, P. Majhi, C. O. Chui, M. R. Visokay, J. J. Chambers, L. Colombo, B. M. Clemens, and Y. Nishi,, Characteristics and Mechanism of Tunable Work Function Gate Electrodes Using a Bilayer Metal Structure on SiO2 and HfO2,, IEEE Electron Device Letters, 2005, 26 (7), 445-447.
A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, Fabrication of High-Quality p-MOSFET in Ge Grown Heteroepitaxially on Si, IEEE Electron Device Letters, 2005, 26 (5), 311-313.
C. O. Chui, L. Kulig, J. Moran, W. Tsai, and K. C. Saraswat, Germanium n-type Shallow Junction Activation Dependences, Applied Physical Letters, 2005, 87 (9).
C. O. Chui, D.-I. Lee, A. A. Singh, P. A. Pianetta, and K. C. Saraswat,, Zirconia-germanium interface photoemission spectroscopy using synchrotron radiation , Journal of Applied Physics , 2005, 97 (11), 113518.
C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, Atomic Layer Deposition of High-k Dielectric for Germanium MOS Applications―Substrate Surface Preparation, IEEE Electron Device Lett, 2004, 25 (5), 274-276.
A. Nayfeh, C. O. Chui, K. C. Saraswat, T. Yonehara,, Effects of Hydrogen Annealing on Heteroepitaxial-Ge Layers on Si: Surface Roughness and Electrical Quality, Applied Physical Letters, 2004, 85 (14), 2815-2817.
H. Kim, P. C. McIntyre, C. O. Chui, K. C. Saraswat, and S. Stemmer, Engineering Chemically Abrupt High-k Metal Oxide/Silicon Interfaces Using An Oxygen-Gettering Metal Overlayer, J. Appl. Phys, 2004, 96 (6), 3467-3472.
M. S. Bakir, C. O. Chui, A. K. Okyay, K. C. Saraswat, and J. D. Meindl, Integration of Optical Polymer Pillars Chip I/O Interconnections with Si MSM Photodetectors, IEEE Trans. Electron Devices, 2004, 51 (7), 1084-1090.
H. Kim, P. C. McIntyre, C. O. Chui, K. C. Saraswat, and M.-H. Cho, Interfacial Characteristics of HfO2 Grown on Nitrided Ge (100) Substrates by Atomic-Layer Deposition, Applied Physical Letters, 2004, 85 (14), 2902-2904.
C. O. Chui, F. Ito, and K. C. Saraswat, Scalability and Electrical Properties of Germanium Oxynitride MOS Dielectrics, IEEE Electron Device Lett, 2004, 25 (9), 613-615.
D. Chi, C. O. Chui, K. C. Saraswat, B. B. Triplett, and P. C. McIntyre, Zirconia Grown by Ultraviolet Ozone Oxidation on Germanium (100) Substrates, J. Appl. Phys, 2004, 96 (1), 813-819.
C. O. Chui, K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, and K. C. Saraswat, Activation and Diffusion Studies of Ion-Implanted p and n Dopants in Germanium, Appl. Phys. Lett.,, 2003, 83 (16), 3275-3277.
C. O. Chui, A. K. Okyay, and K. C. Saraswat, Effective Dark Current Suppression with Asymmetric MSM Photodetectors in Group IV Semiconductors, IEEE Photon. Technol. Lett, 2003, 15 (11), 1585-1587.
H. Kim, C. O. Chui, K. C. Saraswat, and P. C. McIntyre, Local Epitaxial Growth of ZrO2 on Ge (100) Substrates by Atomic Layer Epitaxy, Appl. Phys. Lett, 2003, 83 (13), 2647-2649.
C. O. Chui, S. Ramanathan, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, Germanium MOS Capacitors Incorporating Ultrathin High-k Gate Dielectric, IEEE Electron Device Lett, 2002, 23 (8), 473-475.